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L5973AD
2A SWITCH STEP DOWN SWITCHING REGULATOR
1

GENERAL FEATURES
2A INTERNAL SWITCH OPERATING INPUT VOLTAGE FROM 4.4V TO 36V 3.3V / (2%) REFERENCE VOLTAGE OUTPUT VOLTAGE ADJUSTABLE FROM 1.235V TO 35V LOW DROPOUT OPERATION: 100% DUTY CYCLE 500KHz INTERNALLY FIXED FREQUENCY VOLTAGE FEEDFORWARD ZERO LOAD CURRENT OPERATION INTERNAL CURRENT LIMITING INHIBIT FOR ZERO CURRENT CONSUMPTION SYNCHRONIZATION PROTECTION AGAINST FEEDBACK DISCONNECTION THERMAL SHUTDOWN
Figure 1. Package
HSOP8 (Exposed pad)
Table 1. Order Codes
Part Number L5973AD L5973ADTR Package HSOP8 HSOP8 in Tape & Reel
1.1 APPLICATIONS: CONSUMER: STB, DVD, TV, VCR,CAR RADIO, LCD MONITORS NETWORKING: XDSL, MODEMS,DC-DC MODULES COMPUTER: PRINTERS, AUDIO/GRAPHIC CARDS, OPTICAL STORAGE, HARD DISK DRIVE INDUSTRIAL: CHARGERS, CAR BATTERY DC-DC CONVERTERS
switching regulator with a switch current limit of 2A so it is able to deliver more than 1.5A DC current to the load depending on the application conditions. The output voltage can be set from 1.235V to 35V. The high current level is also achieved thanks to an SO8 package with exposed frame, that allows to reduce the Rth(j-amb) down to approximately 40C/W The device uses an internal P-Channel D-MOS transistor (with a typical of 200m) as switching element to avoid the use of bootstrap capacitor and guarantee high efficiency. An internal oscillator fixes the switching frequency at 500KHz to minimize the size of external components. Having a minimum input voltage of 4.4V only, it is particularly suitable for 5V bus, available in all computer related applications. Pulse by pulse current limit with the internal frequency modulation offers an effective constant current short circuit protection.
2
DESCRIPTION
The L5973AD is a step down monolithic power Figure 2. Test and Application Circuit
3.3V VIN = 4.4V to 35V VREF VCC SYNC. C1 10F 35V CERAMIC COMP C4 22nF C3 220pF R3 4.7K 6 8 2 4 INH
1
OUT
L1 15H D1 STPS340U
VOUT=3.3V
L5973AD
3 7 5 FB GND
R1 5.6K
C2 330F 10V
R2 3.3K
D03IN1453
December 2004
Rev. 3 1/14
L5973AD
Table 2. Thermal Data
Symbol Rth (j-amb) Parameter Thermal Resistance Junction to ambient Max. Value 40 (*) Unit C/W
(*) Package mounted on board
Figure 3. Pin Connection (top view)
OUT SYNC INH COMP 1 2 3 4
D98IN955
8 7 6 5
VCC GND VREF FB
Table 3. Pin Description
N. 1 2 Name OUT SYNC Regulator Output. Master/Slave Synchronization. When it is open, a signal synchronous with the turn-off of the internal power is present at the pin. When connected to an external signal at a frequency higher than the internal one, then the device is synchronized by the external signal. Connecting together the SYNC pin of two devices, the one with the higher frequency works as master and the other one, works as slave. A logical signal (active high) disables the device. With IHN higher than 2.2V the device is OFF and with INH lower than 0.8V, the device is ON. If INH is not used the pin must be grounded. When it is open, an internal pull-up disables the device. Description
3
INH
4 5
COMP E/A output to be used for frequency compensation. FB Stepdown feedback input. Connecting the output voltage directly to this pin results in an output voltage of 1.235V. An external resistor divider is required for higher output voltages (the typical value for the resistor connected between this pin and ground is 4.7K). Reference voltage of 3.3V. No filter capacitor is needed to stability. Ground. Unregulated DC input voltage.
6 7 8
VREF GND VCC
Table 4. Absolute Maximum Ratings
Symbol V8 V1 I1 V4, V5 V3 V2 Ptot Tj Tstg Input Voltage Output DC voltage Output peak voltage at t = 0.1s Maximum output current Analog pins INH SYNC Power dissipation at Tamb 60C Operating junction temperature range Storage temperature range Parameter Value 40 -1 to 40 -5 to 40 int. limit. 4 -0.3V to VCC -0.3 to 4 2.25 -40 to 150 -55 to 150 V W C C V Unit V V V
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L5973AD
Table 5. Electrical Characteristics (Tj = 25C, VCC = 12V, unless otherwise specified.)
Symbol VCC RDSON Il fs Parameter Operating input voltage range Mosfet on Resistance Maximum limiting current Switching frequency Duty cycle DYNAMIC CHARACTERISTICS (see test circuit ). V5 Iqop Iq Iqst-by INHIBIT INH Threshold Voltage ERROR AMPLIFIER VOH VOL Io source Io sink Ib gm High level output voltage Low level output voltage Source output current Sink output current Source bias current DC open loop gain Transconductance RL = Icomp = -0.1mA to 0.1mA VCOMP = 1.9V VCC = 4.4V to 36V VCC = 4.4V to 36V Vsync = 0.74V Vsync = 2.33V Isource = 3mA no load, Vsync = 1.65V
(1)
Test Condition Vo = 1.235V; Io = 2A VCC = 4.4V to 36V
Min. 4.4
Typ. 0.250
Max. 36 0.5
Unit V A KHz
2 0
2.3 500 100 1.235 90 5 7 2.7 50 100 0.8 1.25
% V % mA mA A V V V
Voltage feedback Efficiency Total Operating Quiescent Current Quiescent current Total stand-by quiescent current
4.4V < VCC < 36V VO = 5V, VCC = 12V
1.220
DC CHARACTERISTICS Duty Cycle = 0; VFB = 1.5V Vinh > 2.2V Device ON Device OFF VFB = 1V VFB = 1.5V VCOMP = 1.9V; VFB = 1V VCOMP = 1.9V; VFB = 1.5V 200 1 50 300 1.5 2.5 57 2.3 4 2.2 3.5 0.4
V A mA A dB mS
SYNC FUNCTION High Input Voltage Low Input Voltage Slave Sink Current Master Output Amplitude Output Pulse Width REFERENCE SECTION Reference Voltage IREF = 0 to 5mA VCC = 4.4V to 36V Line Regulation Load Regulation Short Circuit Current
Note: 1. Guaranteed by design
2.5 0.11 0.21 2.75 0.20 3.234 3.2 3 0.35 3.3 3.3 5 8 10 18
VREF 0.74 0.25 0.45
V V mA mA V s
3.366 3.399 10 15 30
V V mV mV mA
IREF = 0mA VCC = 4.4V to 36V IREF = 0 to 5mA
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L5973AD
3
FUNCTIONAL DESCRIPTION
The main internal blocks are shown in Fig. 1, where is reported the device block diagram. They are: A voltage regulator that supplies the internal circuitry. From this regulator, a 3.3V reference voltage is externally available. A voltage monitor circuit that checks the input and internal voltages. A fully integrated sawtooth oscillator whose frequency is500KHz Two embedded current limitations circuitries which control the current that flows through the power switch. The Pulse by Pulse Current Limit forces the power switch OFF cycle by cycle if the current reaches an internal threshold, while the Frequency Shifter reduces the switching frequency in order to strongly reduce the duty cycle. A transconductance error amplifier. A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to drive the internal power. An high side driver for the internal P-MOS switch. An inhibit block for stand-by operation. A circuit to realize the thermal protection function. Figure 4. Block Diagram
VCC
TRIMMING
VOLTAGES MONITOR SUPPLY THERMAL SHUTDOWN
VREF BUFFER
VREF
1.235V 3.5V PEAK TO PEAK CURRENT LIMIT
INH COMP FB 1.235V SYNC
INHIBIT
E/A + + -
PWM
D
Q DRIVER FREQUENCY SHIFTER LPDMOS POWER
Ck
OSCILLATOR
GND
OUT
D00IN1125
3.1 POWER SUPPLY & VOLTAGE REFERENCE The internal regulator circuit (shown in Figure 2) consists of a start-up circuit, an internal voltage Preregulator, the Bandgap voltage reference and the Bias block that provides current to all the blocks. The Starter gives the start-up currents to the whole device when the input voltage goes high and the device is enabled (inhibit pin connected to ground). The Preregulator block supplies the Bandgap cell with a preregulated voltage VREG that has a very low supply voltage noise sensitivity.
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L5973AD
3.2 VOLTAGES MONITOR An internal block senses continuously the Vcc, Vref and Vbg. If the voltages go higher than their thresholds, the regulator starts to work. There is also an hysteresis on the VCC (UVLO). Figure 5. Internal Regulator Circuit
VCC
STARTER
PREREGULATOR VREG BANDGAP
IC BIAS
D00IN1126
VREF
3.3 OSCILLATOR & SYNCHRONIZATOR Figure 6 shows the block diagram of the oscillator circuit. The Clock Generator provides the switching frequency of the device that is internally fixed at 500KHz. The frequency shifter block acts reducing the switching frequency in case of strong overcurrent or short circuit. The clock signal is then used in the internal logic circuitry and is the input of the Ramp Generator and Synchronizator blocks. The Ramp Generator circuit provides the sawtooth signal, used to realize the PWM control and the internal voltage feed forward, while the Synchronizator circuit generates the synchronization signal. Infact the device has a synchronization pin that can works both as Master and Slave. As Master to synchronize external devices to the internal switching frequency. As Slave to synchronize itself by external signal. In particular, connecting together two devices, the one with the lower switching frequency works as Slave and the other one works as Master. To synchronize the device, the SYNC pin has to pass from a low level to a level higher than the synchronization threshold with a duty cycle that can vary approximately from 10% to 90%, depending also on the signal frequency and amplitude. The frequency of the synchronization signal must be at least higher than the internal switching frequency of the device (500KHz).
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L5973AD
Figure 6. Oscillator Circuit
FREQUENCY SHIFTER
CLOCK
t
Ibias_osc CLOCK GENERATOR RAMP GENERATOR
RAMP
SYNCHRONIZATOR
D00IN1131
SYNC
3.4 CURRENT PROTECTION The L5973AD has two current limit protections, pulse by pulse and frequency fold back. The schematic of the current limitation circuitry for the pulse by pulse protection is shown in figure 7. The output power PDMOS transistor is split in two parallel PDMOS. The smallest one has a resistor in series, RSENSE. The current is sensed through Rsense and if reaches the threshold, the mirror is unbalanced and the PDMOS is switched off until the next falling edge of the internal clock pulse. Due to this reduction of the ON time, the output voltage decreases. Since the minimum switch ON time (necessary to avoid false overcurrent signal) is not enough to obtain a sufficiently low duty cycle at 500KHz, the output current, in strong overcurrent or short circuit conditions, could increase again. For this reason the switching frequency is also reduced, so keeping the inductor current under its maximum threshold. The Frequency Shifter (see fig. 6) depends on the feedback voltage. As the feedback voltage decreases (due to the reduced duty cycle), the switching frequency decreases too. Figure 7. Current Limitation Circuitry
VCC IOFF DRIVER A1 A2 IL RSENSE RTH
OUT A1/A2=95 I PWM
D00IN1134
I
NOT
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L5973AD
3.5 ERROR AMPLIFIER The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose non inverting input is connected to the internal voltage reference (1.235V), while the inverting input (FB) is connected to the external divider or directly to the output voltage. The output (COMP) is connected to the external compensation network. The uncompensated error amplifier has the following characteristics:
Transconductance Low frequency gain Minimum sink/source voltage Output voltage swing Input bias current 2300S 65dB 1500A/300A 0.4V/3.65V 2.5A
The error amplifier output is compared with the oscillator sawtooth to perform PWM control. 3.6 PWM COMPARATOR AND POWER STAGE This block compares the oscillator sawtooth and the error amplifier output signals generating the PWM signal for the driving stage. The power stage is a very critical block cause it has to guarantee a correct turn on and turn off of the PDMOS. The turn on of the power element, or better, the rise time of the current at turn on, is a very critical parameter to compromise. At a first approach, it looks like the faster it is the rise time, the lower are the turn on losses. But there is a limit introduced by the recovery time of the recirculation diode. In fact when the current of the power element equals the inductor current, the diode turns off and the drain of the power is free to go high. But during its recovery time, the diode can be considered as an high value capacitor and this produces a very high peak current, responsible of many problems: Spikes on the device supply voltage that cause oscillations (and thus noise) due to the board parasitics. Turn on overcurrent causing a decrease of the efficiency and system reliability. Big EMI problems. Shorter freewheeling diode life. The fall time of the current during the turn off is also critical. In fact it produces voltage spikes (due to the parasitics elements of the board) that increase the voltage drop across the PDMOS. In order to minimize all these problems, a new topology of driving circuit has been used and its block diagram is shown in fig. 8. The basic idea is to change the current levels used to turn on and off the power switch, according with the PDMOS status and with the gate clamp status. This circuitry allow to turn off and on quickly the power switch and to manage the above question related to the freewheeling diode recovery time problem. The gate clamp is necessary to avoid that Vgs of the internal switch goes higher than Vgsmax. The ON/OFF Control block avoids any cross conduction between the supply line and ground.
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L5973AD
Figure 8. Driving Circuitry
VCC
Vgsmax IOFF CLAMP GATE
PDMOS DRAIN VOUT L ESR ILOAD
STOP DRIVE DRAIN ON/OFF CONTROL
OFF
ON C ION
D00IN1133
3.7 INHIBIT FUNCTION The inhibit feature allows to put in stand-by mode the device. With INH pin higher than 2.2V the device is disabled and the power consumption is reduced to less than 100A. With INH pin lower than 0.8V, the device is enabled. If the INH pin is left floating, an internal pull up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also Vcc compatible. 3.8 THERMAL SHUTDOWN The shutdown block generates a signal that turns off the power stage if the temperature of the chip goes higher than a fixed internal threshold (150C). The sensing element of the chip is very close to the PDMOS area, so ensuring an accurate and fast temperature detection. An hysteresis of approximately 20C avoids that the devices turns on and off continuously
4
ADDITIONAL FEATURES AND PROTECTIONS
4.1 FEEDBACK DISCONNECTION In case of feedback disconnection, the duty cycle increases versus the maximum allowed value, bringing the output voltage close to the input supply. This condition could destroy the load. To avoid this dangerous condition, the device is turned off if the feedback pin remains floating. 4.2 OUTPUT OVERVOLTAGE PROTECTION The overvoltage protection, OVP, is realized by using an internal comparator, which input is connected to the feedback, that turns off the power stage when the OVP threshold is reached. This threshold is typically 30% higher than the feedback voltage. When a voltage divider is requested for adjusting the output voltage (see test application circuit), the OVP intervention will be set at: R 1 + R2 V OVP = 1.3 -------------------- V FB R2 Where R1 is the resistor connected between the output voltage and the feedback pin, while R2 is between the feedback pin and ground.
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L5973AD
4.3 ZERO LOAD Due to the fact that the internal power is a PDMOS, no boostrap capacitor is required and so, the device works properly also with no load at the output. In this condition it works in burst mode, with random repetition rate of the burst. 4.4 APPLICATION CIRCUIT In figure 9 is shown the demo board application circuit, where the input supply voltage, Vcc, can range from 4.4V to 25V due to the rated voltage of the input capacitor and the output voltage is adjustable from 1.235V to Vcc. Figure 9. Demo board Application Circuit
3.3V VIN = 4.4V to 25V
VREF VCC SYNC.
6 8 2 4 INH
1
OUT
L1 15H D1 STPS2L25U
VOUT=3.3V
L5973AD
3 7 5 FB GND
R1 5.6K
C1 10F 25V CERAMIC
COMP C4 22nF C3 220pF R3 4.7K
C2 330F 6.3V
R2 3.3K
D03IN1454
Table 6. Component List
Reference C1 C2 C3 C4 R1 R2 R3 D1 L1 STPS2L25U DO3316P-153 POSCAP 6TPB330M C1206C221J5GAC C1206C223K5RAC Part Number Description 10F, 25V 330F, 6.3V 220pF, 5%, 50V 22nF, 10%, 50V 5.6K, 1%, 0.1W 0603 3.3K, 1%, 0.1W 0603 4.7K, 1%, 0.1W 0603 2A, 25V 15H, 3A Manufacturer TOKIN Sanyo KEMET KEMET Neohm Neohm Neohm ST COILCRAFT
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L5973AD
Figure 10. Junction Temperature vs. Output Current
Tj(C )
100 90 80 70 60 50 40 30 20 0.2
65 95 90 Efficiency (%) 85 80
Vout=2.5V Vout=3.3V
Figure 12. Efficiency vs. Output Current
Vin=5V Tam b=25C
Vo=3.3V
Vo=2.5V
Vo=1.8V
75 70
Vin=5V
Vout=1.8V
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0.2
0.4
0.6
0.8
1
1.2 Io(A)
1.4
1.6
1.8
2
Io(A )
Figure 11. Junction Temperature vs Output Current
Tj(C ) 110 100 90 80 70 60 50 40 30 20
V o=3.3V
Figure 13. Efficiency vs. Output Current
95
Efficiency (%)
V in=12V Tam b=25C
Vo=5V
90 85 80 75 70 65 Vin=12V
Vout=5V
V o=2.5V
Vout=3.3V
Vout=2.5V
0.2
0.4
0.6
0.8
1
1.2
Io(A )
1.4
1.6
1.8
2
0.2
0.4
0.6
0.8
1
1.2
Io(A)
1.4
1.6
1.8
2
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L5973AD
5
APPLICATION IDEAS
Figure 14. Positive Buck-Boost regulator
VIN=5V Vcc OUT
L1 15uH
D2 STPS2L25U
VOUT=12V/0.6A
8
COMP C1 10uF 10V Ceramic
1 L5973AD
D1 STPS2L25U FB 24k
4 2 6
VREF GND
7
5 3
C2 220pF
C3 22nF R3 4.7k
M1 STN4NE03L
2.7k
C4 100uF 16V
SYNC
INH
3.3V
Figure 15. Buck-Boost regulator
3.3V VIN = 5V VREF VCC SYNC. C1 10F 10V CERAMIC C2 10F 25V CERAMIC COMP C4 22nF C3 220pF R3 4.7K 6 8 2 4 INH 1 OUT D1 STPS2L25U 2.7K FB GND 24K C5 100F 16V L1 15H
L5973AD
3 7 5
VOUT=-12V/ 0.6A
D03IN1455
Figure 16. Dual output voltage with auxiliary winding
N1/N2=2 3.3V VIN = 5V VREF VCC SYNC. C1 10F 25V CERAMIC COMP C3 22nF C2 220pF R3 4.7K D2 1N4148 VOUT1=5V/ 50mA VOUT=3.3V/ 0.5A Lp 22H D1 STPS25L25U FB GND C4 100F 10V C5 47F 10V
6 8 2 4 INH
1
OUT
L5973AD
3 7 5
D03IN1456
Refer to L5973AD application note (AN1723) to have additional information, details, and more application ideas. L5973AD belongs to L597x family. Related part numbers are: L5970D: 1.5A (Isw), 250KHz Step Down DC-DC Converter in SO8 L5972D: 2A (Isw), 250KHz Step Down DC-DC Converter in SO8 L5973D: 2.5A (Isw), 250KHz Step Down DC-DC Converter in HSOP8 In case higher current is needed, the nearest DC-DC Converter family is L497x.
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L5973AD
6
PACKAGE INFORMATION
Figure 17. HSOP8 (Exposed Pad) Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 A2 B C D E e H h L k ddd 5.800 0.250 0.400 1.350 0.100 1.100 0.330 0.190 4.800 3.800 1.270 6.200 0.500 1.270 0.228 0.010 0.016 TYP. MAX. 1.750 0.250 1.650 0.510 0.250 5.000 4.000 MIN. 0.531 0.004 0.043 0.013 0.07 0.189 0.150 0.05 0.244 0.020 0.05 TYP. MAX. 0.069 0.010 0.065 0.020 0.010 0.197 0.157 inch
OUTLINE AND MECHANICAL DATA
0 (min), 8 (max) 0.100 0.010
(1) Dimension D does not include mold flash, protusions or gate burrs shall not exeed 0.15mm (both side).
HSOP8 (Exposed Pad)
Exposed Pad: D1 = 3.1mm E1 = 2.41mm
7195016
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L5973AD
7
REVISION HISTORY
Table 7. Revision History
Date December 2003 January 2004 December 2004 Revision 1 2 3 First Issue Migration to EDOCS dms Added D1 & E1 dimensions in HSOP8 package information. Description of Changes
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L5973AD
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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